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ZEROPLUS USB Logic Analyzer LAP-C(16128)
품절

ZEROPLUS USB Logic Analyzer LAP-C(16128)

(해외배송 가능상품)
기본 정보
상품명 ZEROPLUS USB Logic Analyzer LAP-C(16128)
판매가 770,000원
상품정보 16ch 4Mb Logic Analyzer
상품코드 P0000JTG
수량 수량증가수량감소
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상품명 상품수 가격
ZEROPLUS USB Logic Analyzer LAP-C(16128) 수량증가 수량감소 770000 (  )
총 상품금액(수량) : 0 (0개)
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이벤트

USB Logic Analyzer LAP-C(16128)

Specifications

Sample Rate
Internal Clock (Timing Mode) 100Hz~200MHz
External Clock (State Mode) 100MHz

Threshold Voltages
Bandwidth:75MHz
Working Range: -6V~+6V
Accuracy: ±0.1V

Memory
Memory:4Mbits
Depth(Per Channel):128Kbits (Max 32Mbits for compression)

Trigger
Condition: Pattern/Edge
Trigger Channel : 16 CH
Post Trigger: YES
Trigger Level: 1 Level
Trigger Count: 1~65535

Software Functions
Data Compression : Max 128K bits x 256
Time Base Range : 5ps~10Ms
Language : Chinese (Traditional/Simplified) English
Maximum Trigger Page : 8192 Pages 
Waveforrm Data Display
Filter&Filter Delay
Trigger Delay
Unlimited lncreasing Bar
Automatic Attaching Bar
Automatic Software Upgrade
Data Statistic
Auto-Save
Filter Bar
Protocol Analysis
Protocol Packet List
File Export
Data Contrast : Not support
Latch Function: Not support
Protocol Analyzer Trigger: parallel
Pulse Width Trigger Module : option

Other
Power :USB (DC 5V, 500mA)
Operating System: Windows 2000 / XP(32bits) / Vista / Win 7
Phase Errors: < 1.5ns
Maximum Input Voltage: ±30V
Impedance:500KΩ/10pF
Safety Certification: FCC / CE / WEEE / RoHS /REACH

Extending Channel Capture
Not support

Double Mode
Channels:16 channels 
RAM Sizes: 256K

ItemMinTypicalMax
Working Voltage
DC 4.5VDC 5VDC 5.5V

Current at Rest
200mA

Current at Work
400mA

Power at Rest
1W

Power at Work
2W

Vinput of Testing Channels
- DC30V+ DC30V

Vreference
- DC6V+ DC6V

Impedance
500KΩ/10pF

Working Temperature
5 ℃70 ℃

Storage Temperature
-40 ℃80 ℃

 



 

 Zeroplus Technology issues the patent technology of Signal Filter Delay. The function of the Signal Filter Delay can capture the signals conditionally. For example, the Filter Condition of channel A1 is set as High Level; the differences can be seen obviously by the horizontal windows, and the Filter Delay Setup can make the conditions of the Signal Filter more flexible; users can set the time of the Filter Delay as their requirements.

 

For example: Clients found Bugs in a group of DUT. The content of the Bug is that a read error may be presented while the program tries to read the data. At that moment, users can use the function of the Signal Filter Delay to capture signal conditionally and analyze the Bug further(the Status of the Read is 0X5A, the Command Period of the Read is 10us). According to the function of the Signal Filter Delay, Zeroplus Logic Analyzer can only capture the 10us Command Period to analyze the Bug when the Data of 0X5A is presented.

Trigger Page

Zeroplus Logic Analyzer adds the patent technology of Trigger Page, in other words, the Trigger Page is to page the continuous and long signal data.

Take the set RAM Size as one page, and the position of the trigger point is the first page. After analyzing the data of the first page, users can set the Trigger Page as "2" and restart the Logic Analyzer when the data of the testing board are the same for each time and the setting of the trigger condition is not to be changed; when the Logic Analyzer stops capturing the data and completes the display, the content of the Waveform Display Area is the data of the second page which follows the data of the first page.

 

For example: The RAM Size is set as 32K; the Sampling Frequency is set as 200MHz; the Trigger Page is "1". The end point of the captured signal is 147.465us and the former half part of the data is 0X47. When starting to capture with the same RAM Size and Sampling Frequency and setting the Trigger Page as "2", the start point of the captured data is 147.465us which is the end point of the first page, and users can see the latter part of the data, 0X47.

Trigger Count

 



 

 

 

 


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